1. Field of the Invention
The invention relates to semiconductor chip or die assemblies and, more particularly, to such assemblies wherein a thin-film coupon-type decoupling capacitor is positioned adjacent to the backside of a die. The invention also encompasses methodology for constructing such assemblies.
2. State of the Art
Traditionally, a widely employed chip assembly (sometimes called a die assembly or a semiconductor device assembly) has comprised a die that is attached to a lead frame. The lead frame provides physical support for the die and is used to connect the die with external circuitry. Generally, lead frames are fabricated from a strip of sheet metal by stamping or chemical milling (etching) and are made from various materials depending on cost, fabrication, and functional requirements. The lead frame may have from four to over one hundred leads or pins. After connecting wires are bonded between the die and leads, the die, wires, and inner ends of the lead frame leads are encapsulated with a plastic encapsulant or located in a preformed cavity-type carrier (generally ceramic, or metal if mil-spec packaging standards apply) to complete the chip assembly.
The various leads of the lead frame (or chip assembly) provide paths for different electrical signals. For example, some lead fingers may conduct data signals between the chip assembly and other chip assemblies. Other lead fingers may conduct address signals used to address memory locations in the chip assembly or another chip assembly. Other lead fingers conduct control signals. Still other lead fingers provide paths for power or ground signals. In some chip assemblies, more than one lead finger provides power or ground. In the case of some chip assemblies, multiple lead fingers carrying power signals may be electrically isolated from each other so that the power signals may have different voltage, current, and/or frequency characteristics to satisfy the requirements of different power groups on the same chip. Likewise, multiple lead fingers carrying ground signals may be electrically isolated from each other. Power signals are sometimes referred to as Vcc (or by a similar nomenclature, such as Vccx, Vccq, Vccl, Vcc2). Ground signals are sometimes referred to as Vss (or by a similar nomenclature, such as Vssx, Vssq, Vss1, Vss2).
With each passing year, newly developed dice provide ever-increasing levels of performance in capacity and speed with little increase, or sometimes even a decrease, in size of the overall die. Indeed, progress in that regard has been astounding. In some instances, the increase in capacity occurs as a result of an increase in density or the number of transistors per units area of material. The increase in speed may be facilitated by an increase in clock frequency or smaller rise times.
Increases in capacity and speed are not achieved without attendant disadvantages. For example, a substantial amount of noise may be created by the switching of huge numbers of transistors. The noise is experienced particularly on the power bus (sometimes referred to as Vcc). One solution is to provide a decoupling capacitor between Vcc and ground (sometimes referred to as Vss). The decoupling capacitor(s) provides a path to ground for high frequency signals, thereby removing them from the power bus.
An on-chip decoupling capacitor may be formed by using a MOSFET (metal oxide semiconductor field effect transistor). The more the capacitance needed, the more silicon (or GaAs) space will be consumed. However, there is usually little, if any, excess silicon space on a state-of-the-art die to implement such an approach. Accordingly, decoupling capacitors have generally been placed off the die.
For example, in U.S. Pat. No. 4,680,613 to Daniels et al. (the xe2x80x9c""613 patentxe2x80x9d), a decoupling capacitor 50 is connected between a power lead finger tab 21 and a ground plate 40, in the package but off the die 14. The power lead finger 22 is formed with an opening or cutout opening 55 with a power lead finger tab 21 adjacent to the opening. (Col. 7, line 66 through col. 8, line 20). The lead frame 20 is formed with a central opening without a die attach paddle or paddle supports and a dielectric layer 30 is also formed with a central opening in alignment with the central opening of the lead frame 20, forming a cavity 16 so that a chip or die 14 may be bonded directly to the ground plate 40 which forms a die attach plate. (Col. 7, lines 62-68).
Col. 1 of the ""613 patent discusses problems with inductive impedance created by long parallel lines or runs of adjacent conductive strips or traces formed by the lead frame fingers. The ""613 patent further states that in order to accomplish the various objectives of that invention, the invention provides an improved low inductive impedance dual in-line package for an integrated circuit die incorporating an elongate lead frame formed with a central opening but without a die-attach paddle in the central opening and without paddle supports. A ground plate forms the die-attach plane, parallel with and spaced from the lead frame. (Col. 3, lines 17-25). The ""613 patent also states the decoupling capacitor is contained within the package itself, closer to the chip, thereby minimizing the series inductance of leads across which undesired voltages are generated. (Col. 5, lines 7-11).
U.S. Pat. No. 4,994,936 to Hernandez (the xe2x80x9c""936 patentxe2x80x9d) describes a decoupling capacitor that is attached directly to an IC lead frame and thereafter encapsulated within a molded package along with an IC chip, resulting in a decoupling scheme which is internal to the molded IC package. The ""936 patent also notes advantages in noise decoupling with low inductance and describes a chip package in which a large, thin decoupling capacitor 34 is attached to the bottom surface of a die support platform 22. The decoupling capacitor 34 comprises a dielectric 36 between conductors 38 and 40.
As semiconductor technology progresses, the trend is to employ unpackaged, or xe2x80x9cbare,xe2x80x9d dice secured directly to a carrier substrate, omitting the lead frame and packaging formerly employed. In such so-called xe2x80x9cchip-on-boardxe2x80x9d (COB) configurations comprising multi-chip modules (MCMs), the dice are connected to terminal pads of conductors on the substrate, as by wire bonding, flip-chip bonding or use of a flex circuit dielectric carrying foil-type conductors. Nonetheless, the need for decoupling capacitors continues and must be accommodated.
Referring to FIG. 1 herein, an exemplary prior art MCM 10 includes a die 14 and a die 16 connected to a substrate 20. Dice 14 and 16 may be packaged or unpackaged. Chip capacitors 22A and 22B provide decoupling capacitance for die 14, and may serve different power groups on die 14 if required. Chip capacitors 26A and 26B likewise provide decoupling capacitance for die 16. Another prior art assembly is depicted in FIG. 2 herein, wherein a die 30 is connected to a substrate 32 and is connected to external circuitry through wire bonds 34. Die 30 may be encapsulated with an optional glob top 40. A remote chip capacitor 42 provides decoupling capacitance.
Chip capacitors are effective in providing decoupling capacitance, but take up valuable surface area or xe2x80x9creal estatexe2x80x9d on the printed circuit board or other carrier substrate carrying the dice and decoupling capacitors, particularly in an MCM configuration.
One approach to reducing the substrate real estate is disclosed in U.S. Pat. No. 4,879,631, assigned to the assignee of the present invention. The ""631 patent discloses the use of packaged, surface-mount dice superimposed over surface-mount capacitors in a single in-line memory module (SIMM) configuration. This configuration is not, however, suitable for current state-of-the-art MCMs employing unpackaged, or xe2x80x9cbare,xe2x80x9d dice. Such modules include SIMM as well as dual in-line memory module (DIMM) configurations, as well as other modules employing dice having functions other than memory.
Several decoupling capacitor configurations are disclosed in U.S. Pat. No. 5,095,402 to Hernandez, including the aforementioned remote chip capacitor (FIG. 1A), a decoupling capacitor placed under a packaged die (FIG. 2A), a lead frame-mounted capacitor as in Hernandez ""936 (FIG. 3A), a flat capacitor formed on a base or substrate attached to a lead frame and on which a die is back-mounted (FIG. 4A), and decoupling capacitors flip-chip mounted on the active surface of a die supported by its backside on a lead frame or the carrier (FIGS. 5A, 6A and 12).
U.S. Pat. No. 4,410,905 to Grabbe discloses a chip carrier whereon an interdigitated capacitive electrode structure is employed under the die-attach location on the carrier, the die then being connected to power and ground through buses associated with the capacitor structure. Such an arrangement requires the in situ formation of each capacitor on its chip carrier, and the configuration of the capacitor limits its capacitance and renders the structure susceptible to shorting due to the presence of bubbles or other voids in the glass-type dielectric.
The present invention provides a semiconductor device comprising at least one die having a decoupling capacitor comprising a thin coupon (xe2x80x9ccapacitor couponxe2x80x9d) mounted adjacent its backside and to which it is electrically connected. The coupon comprises at least two electrode plates with a dielectric film disposed therebetween. The coupon adds no significant height to the semiconductor device when it is mounted to a carrier substrate as part of, for example, a SIMM or DIMM, so that adequate clearance remains between adjacent boards when installed in the bays of a personal computer. Additionally, the close proximity of the capacitor coupon to its associated die and the relatively short conductive connections therebetween minimize undesirable inductance and overall impedance attributable to the presence of the capacitor coupon.
In one embodiment, the semiconductor device includes a capacitor coupon mounted to the surface of a carrier substrate such as a printed circuit board and having a semiconductor die back-mounted thereto. The capacitor is of like size and shape to the footprint of the die as mounted, and may include one or more tab-like electrode extensions or projections to which Vss (ground) or Vcc (power) bond pads of the die may be wire-bonded. Alternatively, one of the electrodes may extend beyond one or more side peripheries of the die along one or more entire sides of the die, and provide a bus to which appropriate power or ground bond pads may be wire-bonded. The capacitor coupon is electrically isolated from conductors carried by the substrate, but one of the capacitor electrodes may be electrically connected to the die through a direct conductive connection to the backside of the die. Similarly, the coupon may be placed so that an outer, exposed electrode is intentionally connected to, for example, a ground conductor on the surface of the carrier substrate.
Another embodiment of the invention also employs a capacitor coupon affixed to the backside of a die, but in this instance, the die is configured with conductive bumps on its active surface for facing, or so-called xe2x80x9cflip-chip,xe2x80x9d connection to terminal pads of conductors on the surface of a carrier substrate. Again, one electrode connection may be made directly to the backside of the die, while the other electrode may be connected to a substrate conductor by a wire bond, flex circuit (TAB) connection using conductors carried on a thin dielectric, or a conductive epoxy may be employed.
Yet another embodiment employs a capacitor coupon-backed die in a direct chip attach (DCA) configuration, wherein a die is configured with an edge connection pattern for plugging into a slot in a carrier substrate. Required connections between the active surface of a die and the capacitor electrodes may be made with wire bonds, TAB tape connections, or by deposition of conductive paths over the exterior of the die extending from the active surface to the backside. One or more vias may also extend from the active side of the die and through the die itself to contact one or more of the electrodes of the coupon.
The capacitor coupons of the present invention may be preformed of layers of conductive foil and dielectric, such as a polyimide tape, and dispensed from a stack or a reel for placement on a carrier substrate. If desired, both sides of each coupon may be provided with a preplaced adhesive (conductive or non-conductive, as required) for affixation of each coupon to a carrier substrate and of a die to each coupon.
Alternatively, the capacitor coupons may be formed in desired locations on a carrier substrate such as that of a SIMM or DIMM by conventional semiconductor die fabrication techniques, such as spinning on dielectric layers of liquid polyimide and sputtering aluminum electrode layers. The coupons may similarly be formed by wafer-scale fabrication techniques on a silicon or ceramic substrate, singulated and then placed on a carrier substrate in desired positions and orientations in conventional pick-and-place operations. The coupons may also be formed during fabrication of semiconductor dice on a wafer or other semiconductor substrates by deposition or application of the electrode and dielectric layers to the back of the wafer prior to singulation of the dice therefrom.
The capacitance of each coupon may be altered by varying the mutually cooperative area of the electrodes or varying the distance between the electrodes. The total cooperative area of the electrodes may be enhanced by providing a capacitive structure with numerous layers comprising each electrode, such as by employing a convoluted or folded electrode structure.